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PRELIMINARY
CY23S08
3.3V Zero Delay Buffer
Features
* Zero input-output propagation delay, adjustable by capacitive load on FBK input * Multiple configurations, see Table 2 * Multiple low-skew outputs -- Output-output skew less than 200 ps -- Device-device skew less than 700 ps -- Two banks of four outputs, three-stateable by two select inputs * 10-MHz to 133-MHz operating range * Low jitter, less than 200 ps cycle-cycle (-1, -1H, -4) * Advanced 0.65 CMOS technology * Space-saving 16-pin 150-mil SOIC/TSSOP packages * 3.3V operation * Spread AwareTM The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Table 1. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The CY23S08 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 A of current draw. The PLL shuts down in two additional cases as shown in Table 1. Multiple CY23S08 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY23S08 is available in five different configurations, as shown in Table 2. The CY23S08-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY23S08-1H is the high-drive version of the -1, and rise and fall times on this device are much faster. The CY23S08-2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The CY23S08-2H is the high-drive version of the -2, and rise and fall times on this device are much faster. The CY23S08-3 allows the user to obtain 4X and 2X frequencies on the outputs. The CY23S08-4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications.
Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 250 ps.
Block Diagram
/2
REF
Pin Configuration
PLL
MUX
FBK CLKA1 CLKA2 CLKA3 REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
SOIC Top View
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
Extra Divider (-3, -4)
S2 S1
CLKA4
FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
Select Input Decoding
/2
CLKB1 CLKB2 CLKB3
Extra Divider (-2, -2H, -3)
CLKB4
Cypress Semiconductor Corporation Document #: 38-07265 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised June 03, 2004
PRELIMINARY
Table 1. Select Input Decoding S2 0 0 1 S1 0 1 0 CLOCK A1-A4 Three-State Driven Driven CLOCK B1-B4 Three-State Three-State Driven Driven Bank A Frequency Reference Reference Reference Reference 2 X Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Output Source PLL PLL Reference PLL
CY23S08
PLL Shutdown Y N Y N Bank B Frequency Reference Reference Reference/2 Reference/2 Reference Reference Reference or Reference[1] 2 X Reference 2 X Reference Description
1 1 Driven Table 2. Available CY23S08 Configurations Device CY23S08-1 CY23S08-1H CY23S08-2 CY23S08-2H CY23S08-2 CY23S08-2H CY23S08-3 CY23S08-3 CY23S08-4 Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank A Bank B Bank B Bank A Bank B Bank A or Bank B Signal REF[2] CLKA1[3] CLKA2[3] VDD GND CLKB1[3] CLKB2[3] S2[4] S1[4] CLKB3[3] CLKB4[3] GND VDD CLKA3[3] CLKA4[3] FBK
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Input reference frequency, 5V tolerant input Clock output, Bank A Clock output, Bank A 3.3V supply Ground Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input For more details on Spread Spectrum timing technology, please see Cypress's application note EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.
Spread AwareTM
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization.
Notes: 1. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the CY23S08-2. 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-ups on these inputs.
Document #: 38-07265 Rev. *D
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PRELIMINARY
Maximum Ratings
Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Input Voltage (Except Ref)...............-0.5V to VDD + 0.5V DC Input Voltage REF............................................-0.5 to 7V
CY23S08
Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec.) ....................... 260C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions for CY23S08SC-XX Commercial Temperature Devices[5]
Parameter VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance
[6]
Description
Min. 3.0 0
Max. 3.6 70 30 15 7
Unit V C pF pF pF
Electrical Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[7] Output HIGH Voltage[7] VIN = 0V VIN = VDD IOL = 8 mA (-1, -2, -3, -4) IOL = 12 mA (-1H, -2H) IOH = -8 mA (-1, -2, -3, -4) IOH = -12 mA (-1H, -2H) Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (-1,-2,-3,-4) Unloaded outputs, 33-MHz REF (-1,-2,-3,-4) 2.4 12.0 45.0 70.0 (-1H, -2H) 32.0 18.0 2.0 50.0 100.0 0.4 Test Conditions Min. Max 0.8 Unit V V A A V V A mA mA mA mA
Power-down Supply Current REF = 0 MHz Supply Current
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices [8]
Parameter t1 t1 t1 t1 t1 Name Output Frequency Output Frequency Output Frequency Output Frequency Output Frequency Duty Cycle[7] = t2 / t1 (-1,-2,-3,-4,-1H, -2H) Duty Cycle[7] = t2 / t1 (-1,-2,-3,-4,-1H, -2H) t3 t3 Rise Time[7] (-1, -2, -3, -4) Test Conditions 30-pF load, -1, -1H, -2, -3 devices 30-pF load, -4 devices 20-pF load, -1H device 15-pF load, -1, -2, -3, devices 15-pF load, -4 devices Measured at VDD/2, FOUT = 66.66 MHz 30-pF load Measured at VDD/2, FOUT <66.66 MHz 15-pf load Measured between 0.8V and 2.0V, 15-pF load Min. 10 15 10 10 15 40.0 45.0 50.0 50.0 Typ. Max. 100 100 133.3 140.0 140.0 60.0 55.0 2.20 1.50 Unit MHz MHz MHz MHz MHz % % ns ns
Rise Time[7] (-1, -2, -3, -4) Measured between 0.8V and 2.0V, 30-pF load
Notes: 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. Applies to both Ref Clock and FBK. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. All parameters are specified with loaded outputs.
Document #: 38-07265 Rev. *D
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PRELIMINARY
Parameter t3 t4 t4 t4 t5 Fall Time Fall Time Name Rise Time[7] (-1H, -2H)
[7]
CY23S08
Min. Typ. Max. 1.50 2.20 1.50 1.25 200 150 Unit ns ns ns ns ps ps
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)[8]
Test Conditions Measured between 0.8V and 2.0V, 30-pF load
(-1, -2, -3, -4) Measured between 0.8V and 2.0V, 30-pF load (-1H, 2H) Measured between 0.8V and 2.0V, 30-pF load All outputs equally loaded All outputs equally loaded
Fall Time[7] (-1, -2, -3, -4) Measured between 0.8V and 2.0V, 15-pF load
[7]
Output to Output Skew on same Bank (-1)[7] Output to Output Skew on same Bank (-1H,-2,-2H,-3)[7] Output to Output Skew on same Bank (-4)[7] Output to Output Skew (-1H, -2H) Output Bank A to Output Bank B Skew (-1,-2, -3) Output Bank A to Output Bank B Skew (-4) Output Bank A to Output Bank B Skew (-1H)
All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded -250 0 0 1
100 200 300 215 250 +275 700
ps ps ps ps ps ps ps V/ns
t6 t7 t8 tJ
Delay, REF Rising Edge to Measured at VDD/2 FBK Rising Edge[7] Device to Device Skew[7] Output Slew Rate[7] Cycle to Cycle Jitter[7] (-1, -1H) Cycle to Cycle Jitter[7] (-2) Cycle to Cycle Jitter[7] (-2) Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on -1H, -2H device using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15, 30-pF loads: 133 MHz, 15-pF load Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 66.67 MHz, loaded outputs 15,30-pF loads Stable power supply, valid clocks presented on REF and FBK pins
125 300 400 200 1.0
ps ps ps ps ms
tJ tLOCK
Cycle to Cycle Jitter[7] (-3,-4) PLL Lock Time[7]
Switching Waveforms
Duty Cycle Timing
t1 t2 1.4V 1.4V 1.4V
All Outputs Rise/Fall Time
3.3V 0V
OUTPUT
2.0V 0.8V t3
2.0V 0.8V t4
Document #: 38-07265 Rev. *D
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PRELIMINARY
Switching Waveforms (continued)
Output-Output Skew
OUTPUT 1.4V
CY23S08
OUTPUT t5
1.4V
Input-Output Propagation Delay
INPUT VDD/2
FBK t6
VDD/2
Device-Device Skew
VDD/2
FBK, Device 1
FBK, Device 2 t7
VDD/2
Test Circuits
Test Circuit # 1 VDD 0.1 F OUTPUTS V DD 0.1 F GND GND 0.1 F CLK OUT C LOAD Test Circuit # 2 V DD 0.1 F OUTPUTS 1 K V DD GND GND 1 K
CLK out 10 pF
Test Circuit for all parameters except t8
Test Circuit for t8, Output slew rate on -1H device
Document #: 38-07265 Rev. *D
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PRELIMINARY
Ordering Information
Ordering Code CY23S08SC-1 CY23S08SC-1T CY23S08SC-1H CY23S08SC-1HT CY23S08ZC-1H CY23S08ZC-1HT CY23S08SC-2 CY23S08SC-2T CY23S08SC-2H CY23S08SC-2HT CY23S08SC-3 CY23S08SC-3T CY23S08SC-4 CY23S08SC-4T Package Name S16 S16 S16 S16 Z16 Z16 S16 S16 S16 S16 S16 S16 S16 S16 Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel
CY23S08
Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial
Package Drawings and Dimensions
16-Lead (150-Mil) SOIC S16
PIN 1 ID
8
1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. 9 16 SZ16.15 LEAD FREE PKG.
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
Document #: 38-07265 Rev. *D
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PRELIMINARY
Package Drawings and Dimensions (continued)
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
PIN 1 ID
1
CY23S08
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
51-85091-*A
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-07265 Rev. *D
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
Document History Page
Document Title: CY23S08 3.3V Zero Delay Buffer Document Number: 38-07265 REV. ** *A *B *C *D ECN NO. 110530 122863 130951 204201 231100 Issue Date 12/02/01 12/20/02 11/26/03 See ECN See ECN Orig. of Change SZV RBI RGL RGL RGL Description of Change Change from Spec number: 38-01107 to 38-07265
CY23S08
Added power-up requirements to operating conditions information. Corrected the Switching Characteristics parameters to reflect the W152 device and new characterization. Corrected the Block Diagram Fixed Typo in table 2.
Document #: 38-07265 Rev. *D
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